The present invention relates generally to semiconductor memories, and, more particularly, to semiconductor read-only-memory (ROM) cell array structure.
Semiconductor ROM is a type of solid state memory which is fabricated with desired data permanently stored in it. Each ROM cell has typically just one transistor either in an “on” state or an “off” state when being selected by a word-line and a bit-line. Word-lines are typically coupled to the gates of the cell transistors. Bit-lines are typically coupled to the drains of the cell transistors while sources thereof are coupled typically to a ground (VSS). Then the “on” or “off” state depends on whether the path of the bit-line to the VSS through a particular cell transistor is electrically connected or isolated. Such path can be determined by a mask, such as contact, via or active (OD). For instance, when a source contact to the VSS is absent for a cell transistor, the cell transistor is in an “off” state.
The cell state is detected by a sense amplifier which translate the “on” or “off” state into a logic “1” or a logic “0”, respectively, or vice versa. The sense amplifier can detect either voltage or current. A difference, either voltage or current, between the cell transistor's “on” and “off” states should be as large as possible, so that the sense amplifier can quickly and correctly detects the state. In a traditional ROM cell, the difference is largely determined by the cell transistor's channel width and channel length. When processing technology enters nanometer era, the cell transistor's channel width and channel length exhibit a significant sensitivity to its layout environments, among which are poly spacing effect (PSE) and shallow-trench-isolation (STI) stress effect (LOD) and strain effect. These effects may significantly affect the channel width and channel length, and hence lower the cell transistor's sensing margin. Increasing transistor size (cell size) or decreasing memory's operation speed can compensate layout environmental effects, but they impact product cost or performance.
FIG. 1A is a schematic diagram illustrating a conventional ROM cell array which has two exemplary memory cells 110[i] and 110[i+1]. In memory cell 110[i], a NMOS transistor 105[i] has a gate and a drain connected to a word-line (WL[i]) and a bit-line (BL), respectively. A source of the NMOS transistor 105[i] is disconnected from a ground (VSS), i.e., floating, by opening a switch 108[i]. Therefore, when the memory cell 110[i] is selected by activating both the WL[i] and BL, the BL will not detect any current, which may be interpreted as a logic “0”. In memory cell 110[i+1], a NMOS transistor 105[i+1] has a gate and a drain connected to a word-line (WL[i+1]) and the same BL, respectively. A source of the NMOS transistor 105[i+1] is connected to the VSS by closing a switch 108[i+1]. Therefore, when the memory cell 110[i+1] is selected by activating both the WL[i+1] and BL, the BL will detect a conduction current of the NMOS transistor 105[i+1], which may be interpreted as a logic “1”.
FIG. 1B is a layout diagram illustrating a layout implementation of the conventional ROM cell array of FIG. 1A. The NMOS transistor 110[i] has an active region (OD) 120[i], a polysilicon gate 127[i], and a contact 123[i] connecting a drain of the NMOS transistor 110[i] to the BL (not shown). There is no contact in the source area 125[i] of the NMOS transistor 110[i]. This is a particular implementation of opening the switch 108[i] (referring to FIG. 1A). The NMOS transistor 110[i+1] has an active region (OD) 120[i+1], a polysilicon gate 127[i+1], and a contact 123[i+1] connecting a drain of the NMOS transistor 110[i+1] to the BL (not shown). There is a contact 125[i+1] in the source area of the NMOS transistor 110[i+1]. This is a particular implementation of closing the switch 108[i+1] (referring to FIG. 1A).
Referring again to FIG. 1B, the polysilicon word-lines, WL[i] and WL[i+1], may pose the poly spacing effect. In modern silicon processes, an isolation between the OD regions, 120[i] and 120[i+1], is performed by a shallow-trench-isolation (STI), which poses stress effect and strain effect, as the spacing between the OD regions, 120[i] and 120[i+1] is kept at minimum for reducing die size. As discussed earlier, these layout related effects may adversely affect the sensing margins of the memory cells. As such what is desired is ROM cell structure that can alleviate such layout related effects without significantly increasing the size or decreasing the speed of the ROM cell array.